Method of fabrication of MOS transistors having electrodes of metallic silicide

ABSTRACT

In a method of fabrication of field-effect transistors having very small dimensions, the gate electrode is formed by a first layer of metallic silicide. Insulating embankments are formed along the lateral edges of the gate and a second layer of metallic silicide is then deposited so as to form the source and drain electrodes. At locations in which the second layer covers the first, planning by planarizing etching is performed so as to produce a structure of flat electrodes in which the gate is separated from the source and drain electrodes by a smaller interval than would be possible in the case of separation by photoetching.

BACKGROUND OF THE INVENTION

The present invention relates to a method for fabrication of integratedcircuits having a high integration density.

The integration density is higher as the dimensions of an elementarytransistor are smaller. It is therefore sought to reduce thesedimensions as far as possible without thereby impairing the electricalproperties of the transistors produced.

Many parameters are to be taken into account in order to obtain goodelectrical properties. At least one of these parameters is particularlyadversely affected by a reduction in dimensions and this parameter isthe electrical conductivity of circuit connections, in particular theelectrical conductivity of the leads which terminate at the gates,sources and drains of field-effect transistors. If the transistor isintended to be of very small size, the contacts of the source and drainelectrodes with the source and drain regions will also be very smalland, similarly, the gate must be very narrow. In that case, however, theability of connections to transmit a high current density decreases,which is detrimental to good operation of the circuit.

It is for this reason that, whereas present-day industrial manufacturingprocesses make considerable use of polycrystalline silicon in thefabrication of the gate electrodes as well as the source and draincontacts and certain interconnections, it is being increasingly soughtto cover the polycrystalline silicon with a layer of metallic silicidewhich has higher conductivity and substantially improves the overallconductivity of connections in respect of given dimensions ofconductors. Furthermore, the present Applicant has endeavored tofabricate transistors in which polycrystalline silicon is not employedat all and in which the gate, source and drain electodes and thefirst-level interconnections are formed entirely of metallic silicidewhich is more conductive than the association of polycrystalline siliconand metallic silicide.

However, it is desirable under these conditions to provide fabricationprocesses which effectively permit a reduction in dimensions oftransistors. In fact, if the use of metallic silicide were to imposefabrication processes which are not conducive to very small dimensions,there would be a risk of losing again any advantage which would havebeen gained in conductivity.

In other words, it is clearly desirable to reduce the resistivity ofinterconnections, of source and drain contacts and of gate electrodesbut it is also desirable to benefit by this reduction in resistivity inorder to increase the integration density of certain circuits or certainportions of circuits.

Another important aspect of the present invention arises from the factthat electrodes of metallic silicide which rests directly onmonocrystalline silicon make it possible to establish Schottky-type(metal/semiconductor) contacts which offer an advantage in certaincases. The concept of field-effect transistors with Schottky contactsfor the source and the drain is described in the article by M. P.Lepselter and S. M. Sze entitled "An insulated-gate field-effecttransistor using Schottky barrier contacts as source and drain",published in "Proceedings of the IEEE, Vol. 56, August 1968, pages1400-1402".

The technical problem presented by these Schottky transistors is theneed to place the source contact (or drain contact) as close as possibleto the gate, failing which a gap exists between the source proper (orthe drain) and the gate-controlled channel, and the transistor cannot bemade suitably conductive.

SUMMARY OF THE INVENTION

The present invention proposes a method of fabrication which makes itpossible to place the source contact (or drain contact) much nearer tothe gate, thereby making it possible not only to produce aSchottky-contact field-effect transistor in a convenient and efficientmanner but also more generally to reduce the dimensions of transistorsto a minimum, whether they are of the Schottky type or not.

The method of fabrication of field-effect transistors in accordance withthe invention comprises the following principal steps:

(a) formation of active regions of monocrystalline silicon separatedfrom each other by insulator regions,

(b) formation on the active regions of a thin insulating layer whichconstitutes the gate insulator of the transistors,

(c) deposition of a uniform layer of metallic silicide,

(d) photoetching of the silicide in a pattern which allows thetransistor gates to remain,

(e) ion implantation of impurities for the formation of drain and sourceregions self-aligned with the gates,

(f) formation of a second insulating layer over the entire activesurface as well as on the vertical and horizontal walls of the gates,

(g) vertical anisotropic etching of said second insulating layer untilthe silicon of the active region is bared outside the transistor gatesso as to allow an insulator embankment (or strip) to remain against thevertical walls of the gates,

(h) uniform deposition of a second layer of metallic silicide,

(i) deposition of an essentially flat layer of a substance which can beetched at the same rate as the tantalum silicide,

(j) uniform etching of said substance until total removal withsimultaneous etching of the second layer of silicide at locationscorresponding to raised portions, the etching process being continueduntil formation of a structure in which the silicide of the first layerand the silicide of the second layer are totally separated electricallyby the insulating embankment.

In this sequence of steps which summarize the general performance of allfabrication operations, attention is more especially directed to thecombination of primary considerations given hereunder:

it is essential to note in the first place that the gate is formed by afirst layer of metallic silicide whilst the source and drain electrodesare formed by a second layer of metallic silicide;

it should next be observed that, whereas the first silicide layer isetched in accordance with a conventional photoetching process whichdefines the gate connections, the second layer is etched in accordancewith a uniform planarizing etching process or in other words a processwhich on the one hand is performed without an etch mask and which on theother hand eliminates substrate surface elevations (in particularsurface elevations formed by overlapping of the second layer on thepatterns of the first layer). It is by means of this uniform planarizingetching process that the two metallic silicide layers are clearlyseparated, an electrical insulation embankment having been provided onthe lateral edges of the gates after formation of the gate pattern.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1 to 10 of the accompanying drawings represent the principalsuccessive steps of a first mode of fabrication in accordance with theinvention and

FIGS. 11 and 12 represent modifications made by adopting a second modeof fabrication.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

The invention will be described mainly in connection with a non-Schottkyn-channel MOS transistor but is applicable to other cases and inparticular to p-channel transistors, to n-type and p-type complementarytransistors on the same substrate, whether of the Schottky type or not.

The starting material consists of a substrate 10 of p-type (for example)monocrystalline silicon in which n-channel field-effect transistors areto be fabricated. In the case of p-channel transistors, the startingsubstrate would be n-type. In the case of n-type and p-typecomplementary transistors on the same substrate, compartments ofopposite type to the substrate would be formed, the transistors of afirst type being formed within the compartments and those of thecomplementary type being formed directly within the substrate outsidethe compartments.

Active regions A are defined and isolated from each other by thickinsulating regions B.

For example, by means of a method of localized thick oxide deposition,there is formed around an active region A a wall 12 of thick siliconoxide (having a thickness of one micron, for example).

The thick oxide extends to a height greater than that of the top surface14 of the active region and to a depth greater than that of saidsurface. A certain topographic relief is therefore formed on the topsurface of the substrate.

It will be noted that, before or after this formation of active regionssurrounded by the walls 12, it is possible to perform conventionaloperations not described here such as a p⁺ type field implantationbeneath the thick walls 12 (region 16) or else depletion or enrichmentimplantations in the active regions or else a deep implantation for theformation of compartments in the case of complementary MOS transistors.

That portion of the insulating walls which projects above the topsurface 14 of the active region A is then planed so as to bring thewalls to the same level or height as the monocrystalline silicon, theinsulation between active regions being achieved by the buried portionof the walls (as shown in FIG. 2).

In order to carry out this surface planarization of the substratesurface, there is performed a flat-surface deposition of resin or glassin suspension in a basic solution ("spin-on glass"), the resin and thecomposition of the glass being chosen so as to ensure that they can beattacked by a suitable etchant at the same rate as the oxide of thewalls 12. Deposition of the resin or of the glass in suspension iscarried out by centrifugation in order to obtain a flat top surface.

The next operation consists in uniform etching (that is to say without amask) of the top surface of the layer for a sufficient length of time toremove the entire thickness of the resin. This is achieved by means of aplasma etching process with a fluorinated compound (CHF₃, for example)to which is added a percentage of oxygen (9%, for example).

The final result then obtained is a flat structure of the type shown inFIG. 2.

In an alternative method, it will be apparent that planarization may bedispensed with while retaining the initial structure of FIG. 1 with thesurface relief formed by the thick oxide regions 12.

The next step consists in forming on the entire surface of the activeregion A an insulating thin film 18 which will serve as gate insulatorfor the insulated-gate field-effect transistors. This thin-film layer ispreferably formed by thermal oxidation of the silicon surface. Saidlayer has a thickness of a few hundreds of angstroms (as show in FIG.3).

It will be possible in some instances to carry out selective etching ofthe thin oxide layer after this step in order to bare themonocrystalline silicon at certain substrate locations. In the majorityof instances, however, the active regions will remain covered by thethin insulating layer 18.

There is then uniformly deposited a metallic silicide layer such as, forexample, tantalum silicide TaSi₂ having a thickness of a few thousandangstroms. The thickness chosen for the deposit will exceed the finalthickness desired for the transistor gates by at least a few hundredangstroms. By way of example in the case of a final gate thickness of2000 angstroms, a deposit having a thickness of 3000 angstroms will bechosen. The silicide is deposited for example by sputtering a target ofsintered tantalum silicide.

A layer 22 of photosensitive resin is then deposited (and can consist ofa multilayer resin which is capable of defining very narrow patterns).

The resin 22 is exposed through a mask which defines a gate pattern andis developed so as to allow resin to remain within the active regionsonly at the gate locations but not at the locations of the source anddrain regions. The resin thus developed is capable of affordingresistance to the tantalum silicide etchants.

The tantalum silicide is then etched by means of a chlorinated plasma,for example, in order to remove the silicide at locations in which it isnot protected by the resin (as shown in FIG. 5).

Prior to removal or after removal of the resin 22, an ion implantationof n⁺ type impurities is carried out in order to define source regions24 and drain regions 26 of the n-channel transistors.

The source and drain regions are consequently self-aligned with respectto the tantalum silicide gate.

In the case of a normal MOS transistor (non-Schottky contacts), theimplantation process will be performed with a dose and a mean energycorresponding to customary practice in the case of polycrystallinesilicon gate transistors. In the case of source and drainSchottky-contact transistors, the implantation will be superficial andtherefore with a low dose and low energy.

For example, in the case of an n-channel Schottky transistor, arseniccan be implanted with an energy of 50 to 80 keV and a dose of 10¹² to10¹³ atoms/cm² so as to obtain a junction depth of approximately 800 to1200 angstroms. The resistivity of the n⁺ surface layer in that case isof the order of 1 to 0.1 ohms-cm.

In the case of a p-channel Schottky transistor formed within an n-typecompartment, it is possible to implant boron with an energy ofapproximately 25 keV with a boron dose of about 10¹² atoms/cm². Thejunction depth is approximately 2500 angstroms and the resistivity is0.1 ohms-cm. Boron may also be implanted by means of boron fluoride withan energy of 25 to 50 keV (junction depth of approximately 1000angstroms).

If the resin has not been removed prior to implantation, it is removedand an insulating substance such as silicon oxide, for example, isdeposited in a uniform layer 28. Deposition is performed in vapor phaseat low pressure so as to obtain a good surface covering at all locationsincluding the abrupt steps 20 of tantalum silicide (as shown in FIG. 6).This deposition process can be plasma-enhanced.

The thickness of said layer 28 is approximately 1000 angstroms. It willbe seen that this thickness governs the spacing between the gate and thesource and drain electrodes.

The layer 28 is then etched uniformly (without a mask) over its entirethickness by adopting a method of vertical anisotropic etching (forexample, reactive-ion etching with a plasma of CHF₃). The etchingprocess is stopped when the monocrystalline silicon surface of theactive region A is bared. Insulating embankments 30 then remain on eachside of the tantalum silicide gate 20. These embankments are theremaining portion of the vertical uniform etch of the oxide layer 28. Inpractice, said embankments form an insulating strip around the entireperiphery of the lateral edges of the gate.

There is then deposited a second layer 32 of metallic silicide (tantalumsilicide). This layer 32 covers the first as well as the monocrystallinesilicon in the source and drain regions while also covering the thickoxide walls. Said layer bears on the insulating embankments 30 atlocations in which the layer 32 extends above the first tantalumsilicide layer 20.

The thickness of the second tantalum silicide layer is smaller than thatof the first layer. By way of example in the case of a thickness of 3000angstroms of the first layer, said second layer has a thickness of 2000angstroms.

There is then uniformly deposited on the entire surface of the substratea layer 34 of planarizing material such as glass in suspension orso-called spin-on glass, for example, which is preferably deposited bycentrifugation so as to obtain a flat surface in the case of this layer.It would be possible to contemplate deposition of an alternativeplanarizing substance such as fluid polyimide (deposited bycentrifugation) or else cathode sputtering of silicon oxide with reversesputtering operations performed alternately with forward sputteringoperations (FIG. 9).

In all cases, the deposited substance must have the property ofpermitting etching at the same time as the metallic silicide of thefirst layer and at the same rate as this latter by making use of acommon etchant.

After deposition of this layer 34, uniform etching of the substrate isperformed with a view to removing this layer over its entire thicknessE1 while at the same time removing the tantalum silicide of the secondlayer 32 at locations in which it extends above the first layer 20.

The most simple method is to stop the simultaneous etching of the layer34 when this latter has entirely disappeared.

A plasma etch with a mixture of chlorinated and fluorinated compoundspermits attack of the spin-on glass and the tantalum silicide at thesame rate. It will be possible to stop the etching process at the timeof spectrometric detection of disappearance of the CO line in theemission spectrum of the products resulting from the etching process.This disappearance indicates that the second tantalum silicide layer(which covers practically the entire substrate) has been bared.

Thus, when the etching process is stopped, there is finally obtained thestructure of FIG. 10 in which the second silicide layer 32 remains onthe greater part of the surface of the substrate but has been removed atlocations in which it covered the first layer, that is to say above thegates.

The gates also remain with a thickness which has been reducedessentially to the thickness of the first layer.

The first layer 20 and the second silicide layer 32 are perfectlyisolated from each other by virtue of the embankments 30 which hadseparated them laterally.

The final surface of the substrate at this stage is practically flat.

The elementary dimension of the transistor considered in the directionof the length of the channel is reduced to the sum of the followingdimensions:

width of the gate which can be the width permitted by the opticalresolution in photolithography, namely of the order of one micron,

width of the embankments: approximately twice 1000 angstroms,

the minimum width which is necessary for the source and drain contacts,bearing in mind the fact that this width must take into account thegate-positioning tolerances at the center of the active region, namelyapproximately twice 1.2 micron.

In the final analysis, the width of the transistor thus obtained issmaller than four microns.

Referring again to FIG. 9 in order to give more details on the method ofetching of the layer 34 and of the raised regions of tantalum silicide,the etching process may be contemplated in two stages.

In a first stage, only the layer 34 must be attacked. It is possible tocarry out a fast reactive-ion etch with fluorinated plasma (CHF₃ or CHF₃+O₂) to a depth almost equal to the thickness E2 of the layer 34 abovethe raised regions of tantalum silicide.

In a second stage, it is necessary to carry out simultaneous etching ofthe layer 34 and of the silicide at the same speed. A low-speed plasmaetch is performed with a mixture of fluorinated compounds (SF₆) andchlorinated compounds (C₂ F₅ Cl or Cl₂).

When the structure of FIG. 10 has been obtained, it is necessary tocarry out photoetching of the metallic silicide in order to define amore precise pattern of interconnections between the active regions. Infact, at the stage of FIG. 10, the entire wafer is covered with thesilicide of the first and second layers, the silicide regions of thefirst layer being completely surrounded by an insulating embankmentwhich separates them from the regions of the second layer. By way ofexample, the object of the silicide etching process will be to separatetwo second-layer portions which are initially joined to each other andwhich must be separated in the final circuit.

The fabrication of the circuit can be continued by further operationssuch as insulating deposits, formation of interconnections on otherlevels and of different conductive materials, passivation, and so on.

In the case of fabrication of CMOS transistors, provision must be madefor splitting-up certain operations in order to perform themindependently on the side corresponding to the n-channel transistors andon the side corresponding to the p-channel transistors. In particular,if the source and drain implantation performed in accordance with FIG. 5has to take place in the presence of the resin 22, it is necessary toensure that etching of the silicide of the first layer 20 is carried outin two separate steps for the n-channel and p-channel transistor gates,each step being followed by a respective n-type or p-type implantation.

If the implantation process is carried out by masking solely by means ofthe silicide gates themselves, (the resin 22 having been removed),etching of the silicide may in that case be performed in a single stepwhereas the implantation is performed in two steps, the transistors ofone channel type being entirely masked by a resin during the source anddrain implantation of the transistors of the other channel type.

In an alternative embodiment of the method in accordance with theinvention, the step corresponding to FIG. 2 is suppressed or, in otherwords, the non-flat surface relief formed by the thick oxide regions 12(FIG. 1) is retained. Exactly the same operations as those describedwith reference to FIGS. 3 to 10 are then performed. Only the resultobtained is different: in the structure of FIG. 10, the silicide 32 ofthe second layer covers practically the entire substrate whilst thesilicide 20 of the first layer covers the remainder, the two layersbeing separated laterally by the insulating embankment 30. In thestructure of FIG. 11, there is no silicide in the thick oxide regions 12and it is only in the active regions A that the silicide 32 of thesecond layer is provided above the source and drain regions and that thesilicide 20 of the first layer is provided for forming the gate, alwayswith an insulating embankment 30 which forms a lateral separationbetween the silicides of the two layers. This structure of FIG. 11results directly from the application of the method described earlierwhen suppressing the step involving planarization of the thick oxide 12at the beginning of the process. It is worthy of note that both thesilicide of the second layer and the silicide of the first layer can nolonger be employed for interconnection of different transistors sincethe silicide is strictly localized within the active regions. Provisionmust accordingly be made for an additional interconnection layer. Sincethe gate will in any case be of very small width as a general rule, itwill be possible only with difficulty to make a contact between gate andadditional interconnection layer. It is for this reason that, as shownin the top view of FIG. 12, the gate will preferably be provided with anextension 134 outside the space which separates the source from thedrain. This extension is located in the active region A or in otherwords above the thin oxide. It will thus be possible to provideconductor contacts 36, 38, 40 respectively (shown in dashed lines) withthe source, drain and gate electrodes. In practice, the shape of theextension 134 will be established by the mask employed for defining theactive regions A and B (the region A will have the extension 134 inaddition to the rectangle corresponding to the transistor proper). Inregard to the mask which defines the gate 20, this mask will also beprovided with an extension which entirely covers the region 134, anypossible overlap being removed at the time of planarizing etching of thesecond silicide layer.

What is claimed is:
 1. A method of fabrication of insulated-gatefield-effect transistors, comprising the following sequence of steps:(a)formation of active regions of monocrystalline silicon separated fromeach other by insulator regions, (b) formation on the active regions ofa thin insulating layer which constitutes the gate insulator of thetransistors, (c) deposition of a uniform layer of metallic silicide, (d)photoetching of the silicide in a pattern which allows the transistorgates to remain, (e) ion implantation of impurities for the formation ofdrain and source regions self-aligned with the gates, (f) formation of asecond insulating layer over the entire active surface as well as on thevertical and horizontal walls of the gates, (g) vertical an isotropicetching of said second insulating layer until the silicon of the activeregion is bared outside the transistor gates so as to allow an insulatorembankment to remain against the vertical walls of the gates, (h)uniform deposition of a second layer of metallic silicide on thestructure remaining after step (g), said second layer having raisedportions formed on said gate electrodes, (i) deposition of anessentially flat layer of a substance which can be etched at the samerate as the metallic silicide, (j) uniform etching of said substanceuntil total removal while simultaneously etching the second layer ofsilicide at locations corresponding to said raised portions during saiduniform etching of said substance, the uniform etching of said substancewith simultaneous etching of said second layer at said raised portionsbeing continued until formation of a structure in which the silicide ofthe first layer and the silicide of the second layer are totallyseparated electrically by the insulating embankment.
 2. A method offabrication of insulated-gate field-effect transistors according toclaim 1, wherein the metallic silicide is tantalum silicide TaSi₂.
 3. Amethod of fabrication of insulated-gate field-effect transistorsaccording to claim 1, wherein step (a) includes localized thickoxidation followed by planarization of the surface of the insulatingwalls by etching of the thick oxide at locations in which said oxide isat a higher level than the surface of the active regions.
 4. A method offabrication of insulated-gate field-effect transistors according toclaim 1, wherein ion implantation of impurities of step (e) is performedwith a sufficiently small dose and a sufficiently low energy to ensurethat a Schottky contact is subsequently established between the secondlayer of metallic silicide and the monocrystalline silicon of the activeregions.
 5. A method of fabrication of insulated-gate field-effecttransistors according to claim 1, wherein ion implantation of step (e)is carried out by employing as a mask the silicide gate pattern of thefirst layer covered with a photosensitive resin which also serves todefine the gate pattern at the time of photoetching of step (d).
 6. Amethod of fabrication of insulated-gate field-effect transistorsaccording to claim 1, wherein the substance deposited in step (i) isglass in suspension known as "spin-on" glass.
 7. A method of fabricationof insulated-gate field-effect transistors according to claim 6, whereinthe etching process of step (j) is a plasma etch carried out with amixture of a chlorinated compound and a fluorinated compound.
 8. Amethod of fabrication of insulated-gate field-effect transistorsaccording to claim 7, wherein the mixture comprises carbonhydrofluoride, C₂ H₅ Cl or chlorine Cl₂.
 9. A method of fabrication ofinsulated-gate field-effect transistors according to claim 1, whereinthe depth of deposition of the first metallic silicide layer is greaterthan the thickness of the second metallic silicide layer.
 10. A methodof fabrication according to claim 1, wherein step (a) comprises alocalized thick oxidation resulting in a non-flat substrate surface inwhich the active regions form recessed portions and the insulatingregions form raised portions, wherein the active region includes atransistor region proper (source, drain and gate) and a gate extensionabove a thin oxide region outside the space which separates a sourceregion from a drain region, a contact being made to an interconnectionlayer between transistors by means of the extension aforesaid.